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Honored Contributor
Honored ContributorQsys MM modules used a standalone IP cores?
Hello, Is it possible to use a Qsys module (such as the UART MM component) as a standalone core for a VHDL design? I have a VHDL designa and I"m looking for a basic UART at the moment and in ...
Altera_ForumHonored Contributor
Honored ContributorYes, you can do it that way (I have done the same, with the UART and the SPI, and others). You can build entire systems with Qsys and never use a NIOS or other processor.
You will basically end up writing an Avalon-MM Master module, and then have a controlling state machine: initialize the UART control register, wait for IRQ ->read from RX data register; maybe poll the UART status register, etc. Whatever your application needs. Here is the Altera supplied templates, which are in Verilog not VHDL as you requested: http://www.altera.com/support/examples/nios2/exm-avalon-mm.html
