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I think it is fairly explanatory really.
To elaborate: "There is an 'Error' which is caused because in the system 'System' there is a component 'External_Clocks" which has an interface called 'avalon_clocks_slave' which is required to have an associated reset signal".
So find the component named External_Clocks, which seems to be something you have made (is that correct?). On that component there is the interface mentioned. That is of type Avalon-MM Slave. As per the spec, Avalon-MM interfaces need a reset signal, but you haven't got one. So you need to add a reset signal and associate it with the Avalon-MM slave.
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This component was already there , i didnt made it , when open the qsys file it shows me the following signals on External_Clocks :
clk_in_primary
sys_clk
avalon_clocks_slave
sdram_clk
clk_in_secondary
audio_clk
vga_clk
There is no reset signal , i can create one as it being pulled from a ready made cores ????
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