Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

QSYS changing from Verilog to VHDL

I'm using a modified version of a QSYS processor/peripheral set from an evaluation board as a basis for a new design. I've gotten my design working on the evaluation board using the original Verilog ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I initially gave up and just wrote the top level in Verilog. Even though the files are allegedly generated in VHDL, they don't have the ports needed to connect them to other internal devices. They can, of course, connect directly to external pins, which is the way they are normally used.

I eventually just rewrote my peripherals as avalon devices and dumped them inside the Qsys system.