QSYS changing from Verilog to VHDL

Hi,

Did you get anywhere with this? I am having the same issue.

The Generation Help text states

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You can turn on/off the following synthesis files for generation:

Create HDL design files for synthesis— Creates Verilog or VHDL design files, as specified by the developers of the components and IP cores in the system. The Qsys interconnect fabric uses Verilog HDL code.

--- Quote End ---

Which kind of makes me think it generates Verilog components only.

I would really like a top level SOPC system in VHDL but think I might be stuck

Rgds

Vern