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Altera_Forum
Honored Contributor
Honored ContributorPWM
Who has the PWM example design(a zip file)? Could you send a copy to me ? Thank you very much! my email: [email protected]
Altera_ForumHonored Contributor
Honored ContributorHello,
Opencores has got a PWM/Timer/Counter IP written in Verilog. Because this one is for the Wishbone bus it must be possible to connect the core with the Avalon bus by Custom Component Editor/Interface to User Logic in SOPCB. http://www.opencores.org/projects.cgi/web/ptc/overview (http://www.opencores.org/projects.cgi/web/ptc/overview) Regards, niosIIuser
