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After studing the avalon specification again I have a few question more.
1) Is it correct that a "normal" read or write-access needs two cycles?
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No. If a device has waitrequest low, then a write will be accepted in one cycle. The read command will also be accepted in one cycle. The Avalon specification indicates that a slave cannot deassert wait and assert readdatavalid in the same clock cycle, so the soonest a slave can return read data is one clock after the waitrequest is deasserted, i.e., two clock cycles for a single-read. However, a burst read can overlap the acceptance of the next read command while delivering the read data from a previously accepted command, if your read burst is long enough, then reads are essentially one clock too.
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2) Can I simulate the read and write behaviour with ModelSim? Is there a master aviable?
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Yes, there is a SystemVerilog JTAG-to-Avalon-MM BFM. If you are using the Altera Starter Edition, then your testbench will also need to be in SystemVerilog (or Verilog).
Cheers,
Dave
Honored Contributor
