--- Quote Start ---
I've designed a custom component which acts as an Avalon Slave. This component has a 32-bit result-register. If data are valid or not is indicated by Bit 31 (true (1) = data valid). Now I want to upgrade the component in such a way that read access to the result register clears the valid bit (write 0 to bit 31).
How can i avoid a write acces at the same time to the valid bit? I mean, the avalon master and my IP-Core could try to write at the same time to the register.
Can I use "waitrequest"? The IP-Core updates the register is in a specific state of the fsm. Can I set the waitrequest signal high in this state and everything would be fine? Or has waitrequest an other purpose?
--- Quote End ---
The read or write
command to the register is accepted by the component
deasserting waitrequest. If you
assert waitrequest when your other logic is modifying the register, then you will stall any concurrent access by an Avalon-MM master.
So yes, you can use waitrequest to implement the functionality you want.
Cheers,
Dave
Honored Contributor
