Honored Contributor
Honored ContributorThanks for the reply. The output of the original SPL1 is less helpful I think - less detail.
I tried booting SPL2 and 3 with both the original dtb, and a new dtb provided by Terasic on their SystemCD, from .../SystemCD/Demonstrations/SOC_FPGA/de1_soc_GHRD/soc_system.dtb The output is the same in both, except for the length of the dtb loaded, as quoted in my previous post. Do you happen to have a U-Boot or GDB debug script to display the clock settings? I could include that output too. Here is the boot output using the original SPL1 and the original DTB U-Boot SPL 2013.01.01 (Nov 04 2013 - 19:51:38) BOARD : Altera SOCFPGA Cyclone V Board SDRAM: Initializing MMR registers SDRAM: Calibrating PHY SEQ.C: Preparing to start memory calibration SEQ.C: CALIBRATION PASSED ALTERA DWMMC: 0 U-Boot 2013.01.01 (Oct 24 2013 - 17:40:22) CPU : Altera SOCFPGA Platform BOARD : Altera SOCFPGA Cyclone V Board DRAM: 1 GiB MMC: ALTERA DWMMC: 0 In: serial Out: serial Err: serial Net: mii0 Warning: failed to set MAC address Hit any key to stop autoboot: 0 reading u-boot.scr ** Unable to read file u-boot.scr ** Optional boot script not found. Continuing to boot normally reading zImage 3809104 bytes read in 1283 ms (2.8 MiB/s) reading socfpga.dtb 17119 bytes read in 13 ms (1.3 MiB/s) fpgaintf ffd08028: 00000000 .... fpga2sdram ffc25080: 00000000 .... axibridge ffd0501c: 00000000 .... # # Flattened Device Tree blob at 00000100 Booting using the fdt blob at 0x00000100 Loading Device Tree to 03ff8000, end 03fff2de ... OK Starting kernel ... Booting Linux on physical CPU 0x0 (clean boot)
