Programming .sof file with nios dev kit stratix

Question

Hi. I&amp;#39;ve bought an Altera Nios development Kit Stratix edition, and I want to program my FPGA with a .sof file compiled from a .gdf file. I don&amp;#39;t have any error messages neither while compiling, nor when I program. Loading executes fine, "user" led shines an instant, but just after, the FPGA comes back in his "safe" config, which was already running since power-on or reset. Does someone know where could be the problem, and how to solve it?? Is it due to the Nios core, which I don&amp;#39;t need and which is running on the default configuration?? If someone has any suggestion, I&amp;#39;d be really helped. Thanks

altera_forum · Answer

The problem doesn&amp;#39;t seem to be due to a loading failure, because the system runs when I program another nios config. So, must  there be a nios core in any development programmed on this board??

altera_forum · Answer

Hi Ice_Tiss, It&amp;#39;s a very strange situation. I think u could check if your project pinout uses pins of the development board that could cause the reset of the board.Sorry it&amp;#39;s only an hint  http://forum.niosforum.com/work2/style_emoticons/&lt;#EMO_DIR#&gt;/smile.gif

altera_forum · Answer

I&amp;#39;ve watched my prograzm but I didn&amp;#39;t find any reset used pin. So I don&amp;#39;t understant what happens. Even with a simple 8 bit counter, plugged on board&amp;#39;s leds, the problem is the same.  It seems like if my configuration is not correct and the factory configuration takes back the control. I really don&amp;#39;t know what&amp;#39;s going wrong!

altera_forum · Answer

Make sure that you have the Unused Pins for your Quartus project set to be Inputs Tristated. You can do this as follows after the project is opened in Quartus:

1. Click on Assign --> Device

2. Click on the Device and Pin Options Button

3. Click on the Unused Pins Tab.

4. This should be the first Radio button.

Just to elaborate on why this is:

A feature of the Nios development boards is to demonstrate remote

reconfiguration. This is done via an FPGA I/O which is connected to

the MAX CPLD on the board. The MAX CPLD is programmed to re-configure

the FPGA when the signal is driven low (in this way, the FPGA can send

a signal telling the MAX chip to reconfigure itself). For reference

designs that include this pin and leave it high, or tri-stated, there

is no issue. However, a user design must either drive this pin high

manually, tri-state the pin manually, or leave the pin un-assigned and

tri-state the unused outputs (as Subroto's instructions indicate).

altera_forum · Answer

I found!!!!!

Visibly, there is a pin, on EP1S10 FPGA which must be set at VCC. it's the pin U2 named PLD_RECONFIGREQ_N in the examples.

I don't know why, but once this pin set, the program remains active after the end of loading.

I regret that this is not told in the board's datasheets, or if it is told, it is certainly lost somewhere in the 779 (or more!) datasheet pages!

Thanks guys for your help

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Programming .sof file with nios dev kit stratix

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