Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

Programming .sof file with nios dev kit stratix

Hi. I've bought an Altera Nios development Kit Stratix edition, and I want to program my FPGA with a .sof file compiled from a .gdf file. I don't have any error messages neither while comp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

I found!!!!!

Visibly, there is a pin, on EP1S10 FPGA which must be set at VCC. it's the pin U2 named PLD_RECONFIGREQ_N in the examples.

I don't know why, but once this pin set, the program remains active after the end of loading.

I regret that this is not told in the board's datasheets, or if it is told, it is certainly lost somewhere in the 779 (or more!) datasheet pages!

Thanks guys for your help