--- Quote Start ---
Hi, the code look like:
always @(posedge csi_clk or posedge rsi_reset_n) begin // To read
if (rsi_reset_n) begin
end else if (avs_s0_read) begin
avs_s0_readdata = START;
end else begin
avs_s0_readdata = 0;
end
end
--- Quote End ---
Its look like your code is correct. Still you can replace above code with this one
always @(posedge csi_clk or posedge rsi_reset_n)
begin // To read
if (rsi_reset_n)
begin
avs_s0_readdata <= 0;
end
else
begin
case(avs_s0_address)
2'b00 : avs_s0_readdata <= START;
default : avs_s0_readdata <= 0;
endcase
end
end
Apart from this what is the read and write latency of your Avalon interface.You can find it in your .tcl file.If write latency is zero then your write logic is correct and if your read latency is 1 then your read logic is correct.
I have one doubt regarding
reset.Is it active high or low? From the name of reset it looks like it is active low and you have used it as a active high. You can also find this from your .tcl file.
Also make practice to use non blocking statement for sequential logic.
Regards,
Krupesh
Honored Contributor
