Honored Contributor
Honored ContributorA DMA core could be used for efficient burst transfer between memory locations. See the embedded IP user's guide (http://www.altera.com/literature/ug/ug_embedded_ip.pdf), chapters 25 & 26 for the SGDMA and DMA cores. There's also the modular SGDMA (mSGMDA) available on the wiki (http://www.alterawiki.com/wiki/modular_sgdma), but I don't have any experience with it.
The warning (20028) just means that Quartus II won't use multiple cores to synthesize/fit your design. I.e. it may take a little longer to build the image. The standard edition of Quartus II does support it - but I honestly do see a huge improvement, it still uses 1 core on my quad core xeon for the most part. When you say "Avalon Bridge", are you referring to the pipelined bridge? You can use those to break up your bus if you have a lot of components and you're having trouble meeting timing. If you just have a few peripherals, and a reasonable clock speed, you probably don't have to bother with it.
