Forum Discussion
Altera_Forum
Honored Contributor
20 years agoI restarted "from scratch" using the Verilog reference design. It works fine.
There's a chance I modified the VHDL design quite some time ago. The VHDL design had "unspecified board" selected, and therefore U5 was not a proper reference. I imagine the whole ecos build tripped on this. I went back to SOPC builder, changed it to Nios-Devkit-1S10ES and re-generated. I opened my library (first.ecc) and had the same problems. Actually, that's where I cut-and-pasted the above messages from. Nevertheless, my problem is fixed. Thanks for sanity checking this for me. -Terry