Forum Discussion
Altera_Forum
Honored Contributor
8 years agoHi there, I will ask you a couple of questions just to double check and clarify my understanding of your problem:
Your post lets me to think you are using an example/reference design. If you are, can you specify which example are you using? Where you trying this by using a modified FPGA system? eg: where you using a compiled rbf of your own with modifications with respect to the GHRD? After you re-generated your dtb, did you have to re-compile any parts of your software? FSBL, kernel? Many thanks in advance!