Problems compiling VHDL

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originally posted by lord_redbeard@Apr 14 2006, 09:49 AM

hello,

i'm using the nios ii development kit on a stratix ii board equipped with an ep2s60 fpga.

i need to implement vhdl blocks for image processing. my block needs to read pixels written in memory (about max. 512*512 pixels). i wrote a for-loop in quartus ii 5.0, in a vhdl file, but it doesn't compile. one error occured which is :

"loop must terminate before or at 10 000 iterations".

but 512*512 pixels = 262 144 iterations !

i also tried to create a for-loop from 0 to 9999 and it works. so i thought i could duplicate this for-loop, but it doesn't compile too.

has anyone had the same problem, or does anyone know how to make a 262144 iterations for-loop ?

for the moment, the only solution i got is to make a 128 pixels memory acces in one iteration, but i want to know if a vhdl for-loop is limited to 10 000 iterations.

finally, i also tried to work with while-loops or illimited-loops (with an exit condition), but the problem still remains : 10 000 iterations maximum.

if you know what to do, feel free to answer. if my problem is not clear exposed, feel free to ask questions.

thanks for your reading,

lord_readbeard

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The design is rather interesting for me.

Obviously it&#39;s a large design for single HDL hardware, whether or not VHDL either Verilog will support this logic level compilation is a question you might get answer for this by referring HDL library.

But I have a feeling Quartus II might not to be able to build such a big logic as well as this amount of registers (I think you don&#39;t have access to on chip memory from HDL) in one design.

For design goal&#39;s sake, I will suggest to use DSP builder or system level design methodology. Buffering data will help.

Good luck, or if you have any update please post.

For your reference: Stratix II EP2s60 has total registers : 52,506