Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

problem with sdram on nios2 dev kit

Hi I have some problems getting started with my nios2 dev-kit. The dev kit is a stratix2 EPS2S60 board. I have tried with both verison 5.1 and 6.0 of the dev-tools. In the nios2 ide "g...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

Good news!

I solved the problem.

I adjusted the pll clock phase shift for sdram_clk_out

from default -3.50ns to -4.0ns 

Testing RAM from 0x1000000 to 0x1FFFFFF
 -Data bus test passed
 -Address bus test passed
 -Byte and half-word access test passed
 -Testing each bit in memory device. . .  passed
 -Testing memory using DMA.  passed
Memory at 0x1000000 Okay
Press enter to continue...

Strange that the dafault settings didn't work on a development board...