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Altera_Forum
Honored Contributor
15 years agoOk, I managed to solve the problem I put it here only for completeness.
The problem in fact was produced by my memory, the clock that I were using to fed it was produced by an PLL and was in phase with the clock of the system (100MHz), and that worked fine for the NO-MMU version. But in the MMU version I had to put an delay in the SDRAM clock, which i set to -45 degrees, so the signals to the memory now have time to be set before the clock signal arrived, and then the system started to work OK. I still don't get how the MMU forced the problem, but with the delay both system work without any problem that I can see (yet). Thank for the help.