Honored Contributor
Honored ContributorProblem resolved !
I modified system composition ... in this new working version I included pll, that generated new clock 143mhz for all for other blocks. Before all blocks were clocked by external clock of 50mhz. Apparently the role of pll is crucial. It would be nice to find some source (e.g. book, article) that treats such issues. https://www.alteraforum.com/forum/attachment.php?attachmentid=13359 However while compiling this new system, another issue wondered me. Here is the extract from compiling report: Warning: RST port on the PLL is not properly connected on instance nios_led:u0|nios_led_pll:pll|altera_pll:altera_pll_i|general[0].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock. Quite strange, because as we can state from the Qsys screenshot, the signal reset of the pll block is connected to the clk_reset of the clk block. Thanks.
