Problem with asynchronous reset and booting

I was on vacation.I could not answer

I discuss more thoroughly the project.

The QSYS is composed of:

-> Ddr2 (Altera DDR2 controller).

-> EPCS with HW and SW.

-> On-chip Memory with BOOT.

The EPCS contains 2 versions of HW and SW for both.

The idea is that the boot start the SW of the EPCS.

Analyzing the In System Memory Content Editor the EPCS contains the correct BOOT at first, but after starting the SW its content changes.

Few bytes are changed. Because of this after the reset the NIOS will not start.

If from the In System Memory Content I restored the original BOOT and I effort reset the NIOS starts.

Also I tried during SW debugging the content changes before reaching the main ().

The BSP configuration editor is the picture 1.

The configuration of the on-chip memory is the picture 2.

Image 3 is the comparison of on-chip memory before and after start of SW.