Problem with accessing Avalon MM slave custom logic

I have my custom logic (simple ALU) verilog as below:

case(address)

//2'b00: opcode <= writedata[1:0];

2'b01: data1 <= writedata;

//2'b10: data2 <= writedata;

//default: readdata <= result;

default: readdata <= 32'h87654320;

endcase

Here is the C code in Nios2:

z = IORD(ALU_AVALON_0_BASE,result); //z = *result;

printf("Result is:\t%08x\n\n", z);

I got the correct result for above code.

However if i change the 32'h87654320 to 32'h87654330 or 32'h87654340, the result become 00000000.

This is strange as i have making sure i re-compile everything (both Quartus and Nios).

Please advice whats is going wrong here...