problem switching between nios cores

I was able to make my 2 pll implementation work with the S-core by measuring and adjusting the phase delay. This is good because I won't need to add a jumper to the board. The required phase entry to produce the same 2ns Tsu is very different between the 1pll and 2pll configuration (0ns and -7ns respectively). Looking at the skew with a scope seems the best way, although with time you could try every 2ns increment covering 360deg of phase.

From the data sheet, the sdram should operate@50Mhz with 2clk cas latency instead of the default 3clks I am using now. Any idea if this is worth doing? If it were non-burst memory (or with no cache), removing a wait state could produce a 20% or more performance boost - well worth it. I don't have a good feel for what the ratio of single-cycle to burst access might be, or if the cache makes this irrelevant. Reducing the cas latency makes the the sdram bus more efficient (higher BW) doesn't it?