Forum Discussion
Altera_Forum
Honored Contributor
20 years agoHi,
Have you seen Verify Failed displayed in the IDE console? If this, it is because sdram cannot work. You can set the phase shift in PLL Mega-Wizard, test with -2ns, -3ns or -4ns. Phase shift is changing with system clock frequency. I think reset delay can be deleted. Regard, LiangYi