problem switching between nios cores

I am using the latest: Quartus5.0 with SP1.04,1.17, Nios5.01

My custom board uses the Cyclone EP1C12 and is very similar to the '1C12 eval example.

I am using both plls with a 3/2 ratio to produce 49.5Mhz from the same 33Mhz. One pll for the core and one for sdram. Both Plls were

needed because of an early pinout mistake.

The code is stored in flash but executed from SDram. There is no external sram to run code from.

With the E-core this system has been tested at the 49.5Mhz and at 99Mhz. When trying the S-core or F-core (at either frequency),

my test SW downloads, but I get no output on jtag or uart0, and no debug ability.

Previous posts suggest to look at problems with the PLL(s); either they are not stable, not starting up promptly, or have the

wrong clk delay for the sdram, or the addition of cache creates timing critical back-to-back reads which the E-core did not produce.

The sdram clock itself looks OK. I have a large 2sec reset delay block and I also tried ANDing the pll clklock outputs to insure

stability on reset. All the sdram (MT48LC4M32 -7) timing options are set the same as the eval example, since it is the same chip.

I have no delay on my PLL(s), also just like the example. I would not expect the required clk shift on my board to be very different

from any of the kit boards since layout differences should be less than 1ns tpd. I quickly tried clk delays of 0,-3.5ns, +1.1ns but no go.

Only the E-core works with these settings.

I can't measure the clk delay on the board when using the faster cores because they don't run, but I might be able to measure and adjust it

on my working E-core config. Is this a good plan, or will the clk delays change when if I pop in a different core?