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Altera_Forum's avatar
Altera_Forum
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13 years ago

Problem in getting final output.

hello.... I am trying to build custom peripheral using NIOS II processor on DE 2 board. My application is edge detection of the image using sobel operator. I am using C code for transmitti...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks for the reply.

I have checked my image processing algorithm on Moelsim with testbench. It is working correctly. I have also synthesized the code on Quartus II, it is also synthesized but it takes a long time for synthesizing. And shows the critical warnings which are:

1) Critical Warning (332012): Synopsys Design Constraints File file not found: 'imageedge.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

2) Critical Warning (332148): Timing requirements not met

3) Critical Warning (169085): No exact pin location assignment(s) for 20 pins of 20 total pins

Can you tell me weather my interface code for communicating with Nios II is correct or not.

Once again thank you for your valuable reply.

Thanks & regards.

Divyang