Problem in Generation of write_n, read_n signals in NIOS-II

Hello gupnaval,

A few days ago, i tried to build a qsys custom component. It was my first experience and not easy.

What helped a lot was to dig into the qsys system using the RTL netlist viewer from Quartus.

There i saw the majority of my mistakes: some of the links that were not correct caused by my own verilog errors.

If qsys makes errors during generation, digging into the design with the netlist viewer can help a lot.

Some care has to be taken into accont using qsys / Nios II / the component editor.

After altering your verilog code in the component, if you do not regenerate your Qsys system, the updated .v does not end up in the right directory and the right version does not get compiled.

Best Regads,

Johi.