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I take a look at your C code and I understand what u're trying to do. Read a byte on each interrupt, but the overhead slow down the performance. A hardware solution is the right way. I don't know how to use DMA component of Nios, too.
If you have SRAM in your system ( not SDRAM, SRAM ), you can implement a simple state machine that when it is triggered acquires de sample, store them in RAM and when finishes make it know to the nios processor. The nios can interface with the SRAM ( to read the samples ) with IO ports. This is not an elegant solution but it should work. You can make it with a SDRAM, too, but it is harder.
How many byte are you storing in SDRAM?
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I've already tried your version that works well with sram without niosii. But my principle purpose is to get 2 port access to sdram via nios using c language. I've no any sdram controller core so i decided to pass by nios.
There is a thing that i can't understand: how the nios makes vga core to work? because the min frequency that must be created is 25MHz? so it can generate high frequency and apply it to nios system output. But it's not explained in any altera document. Am I right?
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