Porting PIO C-code from ARM-7 to Nios II (SE1-board) + performance issue.

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I sure would like to understand how a single core can achieve 1.13 MIPS/MHZ. It must complete more than one instruction per cycle, i.e. 2 per cycle about 13% of the time?

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The 1.13 MIPS/MHz are DMIPS/MHz. DMIPS is a calculated value based on the benchmark test. A value >1 does not necessarily mean, that the cpu can perform more than one instruction per cycle. The MIPS/MHz value for the Nios /f core should be less than 1, otherwise NIOS II/f would be a superscalar architecture.