Porting PIO C-code from ARM-7 to Nios II (SE1-board) + performance issue.

--- Quote Start ---

Once again, the 7 to 1 timing applies to a nios ii/e core (this is the core PDP11GY used).

Have a look at the NIOS II performance benchmarks

www.altera.com/literature/ds/ds_nios2_perf.pdf

NIOS II/e 0.15 MIPS/MHz

NIOS II/s 0.64 MIPS/MHz

NIOS II/f 1.13 MIPS/MHz

--- Quote End ---

So all of those things used to get the cycles/loop reduced to 6 do not apply. And knowing the MIPS without knowing the benchmark is meaningless. And the cost budget only covered the NIOSII/e, so PDP11GY could not afford NIOSII/f.

I sure would like to understand how a single core can achieve 1.13 MIPS/MHZ. It must complete more than one instruction per cycle, i.e. 2 per cycle about 13% of the time?