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Let me see ... Nios will do the loop in 6 clocks ... assuming the timing measurement by PDPGY is accurate, then ARM must be doing the loop in 1 clock to get the 7 to 1 timing.
This fails the sanity test.
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Actually for the /e it is more likely to be 12 clocks, and 18 if the 'short' causes an additional 'andi rn,rn,0xffff' instruction.
Not to mention the Avalon MM delays reading the instructions, I suspect the fastest you'll see (from an M9K memory block) is one wait state.
I can't remember the ARM instruction set that well, and don't know the exact timings - the branch cost (particularly mispredicted) will depend very much on the ARM architecture.
So one wait state and 6 clocks for 3 instructions is about a 7:1 timing difference against even a nios /f core.
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