Porting PIO C-code from ARM-7 to Nios II (SE1-board) + performance issue.

The delay() loop should end up being something like:

delay:
        ori r2,r0,<loop count>     #  for a 16bit constant
loop:
        add r2,r2,-1
        bne r0,r2,loop
        ret

With the /f cpu, the add instruction takes 1 clock, the conditional branch (as coded) 2 clocks when going round the loop, and 4 when the loop exits.

It is possible to get the branch to be 1 clock in the loop exit path - by jumping forwards to an unconditional branch and disabling the dynamic branch predictor. In this case the loop would be 4 + 2 clocks.