Honored Contributor
Honored ContributorI'm doing a lot of 64k hdlc channels entirely in software (including bit-stuffing and crc). The problem I have at the moment is getting the data onto and off the fpga. For performance (and minimising the worst case):
- Use the /f core. - Put code and data into tightly coupled memory. - disable the data cache. - disable the instruction cache unless you need it for download. - Don't call anything in libc, and don't use the Altera supplied startup code. (you only need to set sp, gp and et). - Use gcc's __builtin_expect() to control which branches are taken. - Adjust the C source to avoid stalls following memory reads. - Ask your Altera FAE how to disable the dynamic branch predictor. Then, apart from the Avalon MM transfers to your target device, you'll have consistent instruction timings that match those documented.
