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Altera_Forum
Honored Contributor
19 years agoPolling & INTs with NIOS II
Hi, I have 2 cascaded processors with a shared memory. The first processor writes its data in the shared memory and when it finishes, the second processor must be notified that the data is availab...
Altera_Forum
Honored Contributor
19 years agoHi Acer,
I can't help you much with multiple processors and shared RAM as I've never used either, I have enough problems just keeping one processor on it's wheels. As for the PIOs, there should be enough information in the data sheet to figure out what you need to do, apart from installing the interrupt handler. The following may help: /* Setup a 1 bit PIO (input) which interrupts on the falling edge. */ /* you need these includes */# include "system.h"# include "alt_types.h"# include "sys/alt_irq.h"# include "altera_avalon_pio_regs.h" /* initialise the PIO and install the ISR */ void pio1_init(void) { /* Get PIO into known state */ IOWR(PIO1_IRQ_BASE, IORD_ALTERA_AVALON_PIO_IRQ_MASK, 0x00); IOWR(PIO1_IRQ_BASE, IORD_ALTERA_AVALON_PIO_EDGE_CAP, 0x00); IOWR(PIO1_IRQ_BASE, IORD_ALTERA_AVALON_PIO_IRQ_MASK, 0x01); /* register the interrupt function */ alt_irq_register(PIO1_IRQ_IRQ, 0, my_pio1_service); } /* Your ISR function */ void my_pio_service(void* context, alt_u32 id) { /* this clears the source of the interrupt, stops re-entry until next edge */ IOWR(PS2_IRQ_BASE, IORD_ALTERA_AVALON_PIO_EDGE_CAP, 0x00); do_your_stuff_here; } Banx.