Honored Contributor
Honored ContributorHey Banx,
Thanks for ur help, it worked but I am moved to a new problem http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif It's the shared memory + software program controlling PIO. Shared Memory ========== I am using Cyclone1 NIOS II dev. kit, I thought of making CPU1 work from the SDRAM (Inst.+Data) and make CPU2 have an onchipmemory by using the RAM bits (Inst.+Data) and I have also a shared memory in between them as an onchipmemory. The RAM bits aren't enough !!! (294,000 only while I need a lot). My program needs about 380KB. So, I started checking the other memories (SRAM & SDRAM) to be the (Inst.+Data memory for CPU2). * I thought of SRAM coz I need separate memories for both CPUs coz they will be working as pipelined processors i.e working in the same time with different codes. Thus, I connected the SRAM to the inst. & data master of CPU2 but I get a strange message in the board settings saying that "sram/s1/data/data[28] and sram/s1/data/data[12] are in the same bus and shouldn't have the same pin assignment" and so on for the rest of the SRAM pins. * Speaking about the SDRAM, is there a way to divide it between the 2 processors with each working in the same time & using different ranges for their inst. and data, or it can't be done due to sharing same control lines ? Software ===== I have read countbinary.c & I am a bit confused about the method of dealing with PIOs in software especially the part of definitions. Are there certain definitions that must be made for PIOs in the c-file like those in system.h & countbinary.c ?
