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Altera_Forum's avatar
Altera_Forum
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19 years ago

Polling & INTs with NIOS II

Hi, I have 2 cascaded processors with a shared memory. The first processor writes its data in the shared memory and when it finishes, the second processor must be notified that the data is availab...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

Hi Acer,

I was away yesterday so sorry for not replying quicker.

If I understand you correctly, you want CPU1 to control when CPU2 is allowed to perform some kind of task. To do this you have put a 1-bit (o/p) PIO1 on CPU1 and a 1 bit (i/p) PIO2 on CPU2 then joined them together.

I don't see why both CPU's need access to PIO1. I guess you want CPU2 to be able to reset the output on PIO1 after it has recognised the signal to begin processing. If you make PIO2 edge-sensitive then PIO1 only needs to be pulsed by CPU1 (so no need for CPU2 to access it). What I'm saying is having both CPU's able to control PIO1 sounds like a bad idea and probably not necassary (If I've understood your requirement).

I'm not sure that you actually need to assign the PIO lines to physical pins on the device, I think you can just join them together on the schematic. I think you may just be getting a warning from Quartus that you haven't brought the pins out of the device.

I hope this helps a little, but I guess you've already got it working by now.

Banx.