PLL jitter warning

'Having the 50MHz "main" clock and the 50MHz shifted clock coming from the same PLL is exactly what you want to do. '

I thought so, but the refererence design does not do this, and it does not show using the same PLL to provide two different phase shifts.

Looking at the Cyclone device handbook shows my dilemma. My main clock comes in on CLK0 (PLL1), but my sdram is fed by the PLL2 output. Without cuts and jumpers, it looks like I am stuck using both PLLs. How is the synthesis able to eliminate one of the PLLs without breaking the rules spelled out in the handbook?