PLL jitter warning

All that warning means is that c0 is compensated so all others with not be as clean essentially. If you moved the compensation to c1 you would get this warning for c0 instead. A PLL is fed by a dedicated circuit so if you try to route that clock to the other side of the FPGA the tools will tell you this (you wouldn't want to do that anyway).

Having the 50MHz "main" clock and the 50MHz shifted clock coming from the same PLL is exactly what you want to do. Also at 50Mhz you really don't have to worry about jitter (if you were barely passing timing that's a different story though). I recommend you look at the device datasheet and study it's clock network so you know what each PLL can input and output. Judging by the description of the error you get sharing the PLL, you need to take a look at a Nios II Cyclone reference design since I think you are using the same clock pins (one PLL feeds the other in that design using a board trace).