Please help me ......SDRAM DE2

Recently I have came upon these issues you are facing, and believe I can be of some help:

1. Follow this tutorial to integrate the SDRAM memory controller to your NIOS II processor: "Using the SDRAM Memory on Altera’s DE2 Board" (just google it, I can't provide you the link)

2. The SDRAM CLK must have a 3 ns phase delay from the Avalon interface clock. Besides using a PLL with a "-3 ns" delayed output, you must define time constraints accordingly.

3. You can read/write from/to the SDRAM using simple I/O macros, such as:

int val=123;
IOWR( SDRAM_BASE, SOME_OFFSET, val );
val = IORD( SDRAM_BASE, SOME_OFFSET);

4. It is also possible to declare variables in the SDRAM because it is memory mapped, just like the internal SRAM memory. I haven't done that yet, but I have read it from a pdf file I found on google.

5. Something I noticed when I was testing the SDRAM is that there are some memory positions at the beginning and at the end of the memory that don't work properly (at least in my DE2 board). So I only use the following range of addresses:

SDRAM_BASE+2048B < range < SDRAM_BASE+8MB-2048B

As you can see I'm only throwing away 2KB (0.025%)... I was able to successfully write to all other memory positions.

Best Regards,

Thomas.