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Altera_Forum's avatar
Altera_Forum
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19 years ago

Pipelining multiple NIOS II processors

Hi all,

I am working on a project that demands pipelining several processors. I lack experience in the part of multiprocessors. So, I was wondering if anyone has tried before the way of pipelined NIOS II processors, perhaps he\she can guide me.

I imagine the situation as follows:

- let's assume I wanna pipeline 3 processors each performing a different set of codes. Each 2 consecutive processors should have a common memory. The first processor should write the output of its operations in the memory. The second processor should wait until the first processor finishes processing. I thought that the second processor should poll on a flag and here came the problems:

* First assumption is a memory location that is changed once the processing ends. The problem is the second processor can't read from the same memory the first processor is writing in. How can I make it using SOPC?

* Second assumption is: Is there a ready-made function in NIOS II functions that raises a flag when the operation ends and the second processor can see it while both running different programs ?

* If anyone has an idea pls feedback me with it.

- What kit should I buy in this case ? I need about 4 pipelined processors of high performance (Stratix, Stratix II, Cyclone II NIOS II development kits) ?

Thanks in advance . .

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    I hope not to be too much obvious...

    --- Quote Start ---

    originally posted by acer_7@Feb 12 2007, 07:16 AM

    * first assumption is a memory location that is changed once the processing ends. the problem is the second processor can't read from the same memory the first processor is writing in. how can i make it using sopc?

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=21448)

    --- quote end ---

    --- Quote End ---

    You can set a flag in memory after finishing to write on it. For example, cpu_1 is writing whereas cpu_2 is doing something like "while(shared_memory->FLAG != AVALIABLE);". When cpu_1 finishs, it sets shared_memory->FLAG to AVALIABLE. Avalon Interface will warrant the shared memory flag won&#39;t be read and write in the same time by different processors.

    --- Quote Start ---

    originally posted by acer_7@Feb 12 2007, 07:16 AM

    * second assumption is: is there a ready-made function in nios ii functions that raises a flag when the operation ends and the second processor can see it while both running different programs ?

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=21448)

    --- quote end ---

    --- Quote End ---

    You can use interruptions to warn a cpu. PIO cores can solve it.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    Be sure that you take care of cache coherency as well. For example if Nios A modifies data in a shared memory that Nios B uses, Nios B may access a stale copy. The Nios II processor uses a write back cache so before handing data off to another processor be sure to flush the cache (or use another means like cache bypassed pointers or tightly coupled memory).