Performance Issues

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originally posted by shmueld@Jul 11 2006, 10:53 AM

thank you everyone for all your information.

mschmitt, when you stated :-

"nowadays the readdata is a wire with a set of combinatorical logic and now each access is only 1 clock cycle long, regardless of read or write."

what did you mean ?

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With this statement i mean that the oldway i did a avalon slave was :

internal_signal -> DFF -> ReadDatabit

where the internal_signal was combinatorical with the internal signal selected by the address.

Now i have changed that in a way that i have removed the DFF. ReadData is now a wire instead of a reg (in verilog language)

wire [31:0] avs_MyModul_readdata;

assign avs_MyModul_readdata =

( avs_MyModul_address === 6&#39;H00 ) ? { 32&#39;d12345678} :

( avs_MyModul_address === 6&#39;H01 ) ? { 32&#39;d87654321} :

{ 32&#39;d87654321};

Reading from slave address 0 will be 1234567, address 1 will be 87654321 and all others will be 0

this read is only 1 clock cycle long (or short :-) ) no need to assert avs_MyModul_waitrequest

is it now clear to you ?

Michael Schmitt