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Altera_Forum's avatar
Altera_Forum
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19 years ago

Performance Counter offset

Hi, i have a question about the PERFORMANCE COUNTER component. I have the following code to measure the overhead from starting/stoping the counter: PERF_BEGIN (PERFORMANCE_COUNTER_BASE, 1);...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I'm disable the Instruction cache in SOPC CPU and it give me errors. It is set to 2Kbyte of cache. So I enable back in SPOC and tried to add in alt_icache_flush_all() before the performance counter and it still give the different clk count. In my SPOC there is a shared memory between CPU and FPGA. I created a Dual memory port RAM using custom instruction and link to CPU. It has a fix latency. Could this create the different in clk count?