Honored Contributor
Honored ContributorIf your design is complex (i.e. not a minimal system) then I would reduce it (especially any offchip memory/peripheral connections). Here's what I recommend:
Nios II 's' core (with a level 1 OCI core) 8kB of onchip memory sysid peripheral jtag uart Then try running the hello world small software template on it. If that works then start adding offchip devices one by one to figure out which one is breaking your design. If the idea above doesn't work then I would dump an even simplier design in (like an AND gate) to see if that even works. If a dirt simple non-jtag communication design (no OCI, JTAG UART, or SignalTap II) works then I would start looking at your JTAG signals on the PCB for noise. I hope that helps.
