Honored Contributor
Honored ContributorStonie,
<div class='quotetop'>QUOTE </div> --- Quote Start --- If not - any suggestions for a different core (wchich costs less than $2000 on royalties).[/b] --- Quote End --- in my project I use the core from PLD-Applications (www.plda.com) . It's a Master / Target PCI / PCI-X core for 32 or 64 Bit bus-size. I've implemented a PCI-target function, that has access to a shared SRAM on Avalon-Bus, which is the System-RAM. So, I have a small boot loader in EPCS, but the main firmware is loaded via PCI-bus direct into the SRAM (PCI-Space 0). Further I've implemented a master function to transfer data from Avalon via PCI-DMA to the host PCI-Memory. And third, a bidirectional register file (PCI-Target) to communicate (PCI-Space 1). I spent lots of time to implement the target interface PCI <-> Avalon: when PCI requests access to an Avalon device, a wait signal from Avalon is active while the arbitration process is working. If wait ends, the following single cycle is the access cycle to Avalon. But the PCI core needs after the delay phase several PCI-clock cycles until its own access will be processed. In other words, the PCI core expects, that he has got the system bus an indefinite time until its access is done. So this interface to Avalon is not adapted very well. With my interface only 32-Bit transfers are possible, because byteenables from PCI core are valid, several cycles after Avalon access is done. Mike
