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Are both your fifo clocks ok? No glitches? Is your design properly constrained and does it meet all timing requirements?
You can also try and recompile your project after having deleted the db and incremental_db folders. I've seen weird things with the full and empty signals on generated FIFOs when Quartus re-uses parts of a previous compilation (at least on Quartus 10 and 11.1)
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Everything is well constrained, but I am using the older 11.1 quartus. However, I'm using it in such a basic way that I doubt it's on their end.
The nios and fifo clocks come from a pll, however, originally, when I tried feeding the clock directly to the in-port of the fifo, the fifo never saw ANY data. I put the clock bridge in there since it seemed to make sense at the time, but actually, it should work without it so perhaps that's a clue.
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