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Altera_Forum
Honored Contributor
Honored ContributorOnChip Fifo Status Shows simultaneous FULL and EMPTY!
I have a simple Dual-Port 4k On-Chip FIFO, with the out/csr-port connected to the Nios avalon in qsys, and the in-port from external logic. As a test, I have the input pumping incrementing data...
Altera_ForumHonored Contributor
Honored ContributorAre both your fifo clocks ok? No glitches? Is your design properly constrained and does it meet all timing requirements?
You can also try and recompile your project after having deleted the db and incremental_db folders. I've seen weird things with the full and empty signals on generated FIFOs when Quartus re-uses parts of a previous compilation (at least on Quartus 10 and 11.1)
