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Honored Contributor
Honored ContributorOn-Chip Memory instruction corruption
We have a design which uses a NIOS CPU whose instruction code is stored in On-Chip Memory. Most of the time everything works however there are times when the code is changed slightly and either the f...
Altera_ForumHonored Contributor
Honored ContributorYou have some timing problems:
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1100mV 100C Model Setup Summary ; +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+---------------+ ; Clock ; Slack ; End Point TNS ; +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------+---------------+ ; clock100MHz ; -5.337 ; -1273.828 ; ; rgmii_125_tx_clk ; -1.041 ; -4.946 ; On clock100MHz and on rgmii_125_tx_clk you have timing violations (very strong violation on clock100MHz). It is normal that your design does not works.
