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Altera_Forum's avatar
Altera_Forum
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13 years ago

offset binary to signed converter for ADC

Hello I’m neebie in VHDL. I’m trying to build a simple radio receiver: CAN , mult, filter, I Q demod in Cyclone III , with quartus . I ‘m sorry for this question here, be I don’t found solution...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

hello

as most problem , there many solutions..here is mine , simplier for 14 bits than the previous i have done....interresting for partial bus allocation.

ENTITY INVBITBUS14 IS

PORT(

a_bus : IN bit_vector(13 downto 0);

s_bus : OUT bit_vector(13 downto 0));

SIGNAL a13 : BIT;

END INVBITBUS14 ;

ARCHITECTURE dataflow OF INVBITBUS14 IS

BEGIN

a13 <= a_bus(13);

s_bus (13) <= NOT (a13); -- inversion du bit

s_bus(12 DOWNTO 0) <= a_bus(12 DOWNTO 0);

END dataflow ;

Many thanks for your help!!!!!!!!