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Altera_Forum
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14 years ago

non-cacheable instruction memory

Hi at all, I'm new in this forum. I create a Nios II system containing a Nios II/f core, with 2k data cache and 2k instruction cache, and 128k of on chip-memory. I want to run on this system an ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thank you for fast reply. I'm a master student and I have to realize a project on which I must to load a part of assembly program in cacheable instruction memory and the other on non-cacheable instruction memory.

From your reply I understand that all instructions load into tightly coupled memory block are not loaded into instruction cache and the instructions into on-chip memory are loaded in cache, is correct?:confused:

If it is correct, how can I load a part of the assembly program into on-chip memory and the other part on tightly coupled memory block?:confused:

Thank you for your helpfullness.:)

Daniele.