Hi,
Yes, the correct .sof file is downloaded to the FPGA and runs.
Yes, it is the correct sopcinfo file.
Clk (100Mhz) and Reset (high active) are correctly connected and are working.
The Target connection tab shows no target even after multiple refreshes.
I've set the following clock constraints:
create_clock -name {CLK_100MHz} -period 10.000 -waveform { 0.000 5.000 } [get_ports {CLK_100MHz}]
derive_pll_clocks
create_clock -period "30.303 ns" -name {altera_reserved_tck} {altera_reserved_tck}
The altera_reserved_tck constraint is based on this Knowledge Base article.