NIOSV EIC , MPU and MMU ip cores - availability plan & date?

Hi there Intel,

I recently started using the NIOSV cpu on my Terasic DE0-NANO board (featuring Cyclone IV fpga), and just tried to create some example projects to just tinker with and experiment with this new CPU core. (Using Quartus 23.1.1 Standard on Win.)

https://github.com/monkstein88/niosv-example-projects

I recently wanted to implement (add) in the QSYS design a Vector Interrupt Controller and either an MPU (Memory Protection Unit) or MMU (Memory Management Unit) . But I noticed that :

1. It seems that neither of the NIOSV CPU versions supports/features external interrupt controller (EIC) capabilities. Which impacts interrupt handling performance.

2. Neither MPU nor MMU features are available for any type of NIOSV, which blocks the ability to run any bigger OS i.e. Linux on this cpu core.

So, in my opinion, at the moment, it seems the NIOSV core is somewhat limited in its capabilities.

But I just want to ask if you plan and if so when, to include the EIC , MMU and MPU features for the NIOSV?

Thank you,

M.M.