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Altera_Forum
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12 years ago

Nios/qsys address map (beginner)

Hello everyone, As title states, I'm new to alteras Qsys, Nios and related tools. I started with alteras tutorials, creating a simple system with Nios2, pio etc. Then I tried a simple soft...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I had a similar thing happen with a project. When I asked a real EE, he said that I was reading back the residual value on the bus. Since there weren't any pull up/down resisters in the FPGA the value of the internal signals takes some time to go back to the unexcited state. When I added a delay before reading back it was random again.